Developed and scaled IR/EM signoff and PDN handoff methodologies adopted across multiple SoC programs at Arm
and previously at Intel, enhancing design convergence speed and ensuring first-time-right silicon delivery in 5nm/7nm
nodes.
Automated RTL2GDSII workflows and planning processes using Python and Tcl, cutting onboarding efforts by over
40% and enabling consistent flow integration across teams globally
Led cross-functional flow and signoff initiatives, bridging gaps between architecture, CAD, and PD teams—directly
influencing global project delivery timelines and mentoring engineers on best practices.
Automated planning and signoff workflows using Python and Tcl, streamlining integration and reducing onboarding
effort by over 40%